diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index d5cdd7163d7910..166b6dbf46db87 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -10318,8 +10318,10 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
     AddNodeIDNode(ID, Opcode, VTs, Ops);
     void *IP = nullptr;
 
-    if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP))
+    if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP)) {
+      E->intersectFlagsWith(Flags);
       return SDValue(E, 0);
+    }
 
     N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs);
     createOperands(N, Ops);
@@ -10524,8 +10526,10 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
     FoldingSetNodeID ID;
     AddNodeIDNode(ID, Opcode, VTList, Ops);
     void *IP = nullptr;
-    if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP))
+    if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP)) {
+      E->intersectFlagsWith(Flags);
       return SDValue(E, 0);
+    }
 
     N = newSDNode<SDNode>(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTList);
     createOperands(N, Ops);
diff --git a/llvm/test/CodeGen/ARM/dagcombine-drop-flags-freeze.ll b/llvm/test/CodeGen/ARM/dagcombine-drop-flags-freeze.ll
new file mode 100644
index 00000000000000..63e16b03caee6b
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/dagcombine-drop-flags-freeze.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=arm-eabi -o - %s | FileCheck %s
+
+; Ensure poison-generating flags are stripped by the time a freeze operand is visited.
+
+define i1 @drop_flags(i32 noundef %numentries, i64 %cond, i64 %arg) {
+; CHECK-LABEL: drop_flags:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    ldm sp, {r1, r12}
+; CHECK-NEXT:    subs r1, r2, r1
+; CHECK-NEXT:    sbcs r1, r3, r12
+; CHECK-NEXT:    movlo r0, r2
+; CHECK-NEXT:    rsbs r1, r0, #0
+; CHECK-NEXT:    adc r0, r0, r1
+; CHECK-NEXT:    mov pc, lr
+entry:
+  %cmp4 = icmp samesign ult i64 %cond, %arg
+  %conv6 = trunc nuw i64 %cond to i32
+  %spec.select = select i1 %cmp4, i32 %conv6, i32 %numentries
+  %spec.select.fr = freeze i32 %spec.select
+  %cmpz = icmp eq i32 %spec.select.fr, 0
+  ret i1 %cmpz
+}